Woofun AI reports that JEDEC announced the SPHBM4 standard (JESD330-4), which utilizes HBM4 DRAM stacks with a different buffer chip to alleviate AI advanced packaging bottlenecks. This approach aims to maintain HBM4 performance while reducing reliance on constrained advanced packaging solutions.

The standard employs high-speed serial channels, allowing memory placement up to 20 mm away from GPUs, unlike traditional HBM. This expansion increases substrate area requirements and drives demand for high-density ABF substrates with 20 to 28 layers or more, as well as future glass substrates, shifting engineering complexity from silicon interposers to oversized substrates.