Morgan Stanley: AI Chip Surge Tests Power Grids, HBM, and CoWoS Capacity Limits by 2027

Woofun AI reports that Morgan Stanley's latest supply chain assessment reframes the primary constraint for artificial intelligence expansion from semiconductor manufacturing to infrastructure stress testing, specifically highlighting an implied electricity demand of 38GW by 2027. This projection shifts the industry focus from whether GPUs can be produced to whether power grids, cooling systems, and advanced packaging can support the resulting load.

The 38GW figure is derived from a calculation based on approximately 19 million Rubin NVL72 and Rubin Ultra chips, alongside other GPUs and ASICs, projected for delivery by 2027. Assuming an average thermal design power (TDP) of 2kW per unit, the total implied demand reaches 38GW. NVIDIA accounts for the largest share at 16GW, followed by Google with 9GW, AMD with 7GW, AWS with 2GW, and Microsoft, Meta Platforms, and others contributing approximately 1GW combined. This breakdown illustrates the concentrated nature of power consumption among a few key technology leaders.

It is crucial to define this 38GW metric as a stress test rather than an actual operational load. The figure excludes the electricity usage of CPUs, networks, storage systems, cooling mechanisms, and other supporting facilities within data centers. Instead, it serves as a baseline to evaluate whether power infrastructure can keep pace with chip shipments. The constraint is no longer solely about GPU availability but involves the simultaneous implementation of HBM, CoWoS packaging, testing processes, rack delivery, and power access.

Infrastructure bottlenecks extend beyond chip production to grid connectivity, substation construction, data center location selection, and long-term power procurement. Once GPUs or ASICs enter data centers, they require servers, racks, networks, cooling systems, power supplies, and maintenance systems. If infrastructure development lags behind chip shipments, a mismatch may occur where chips arrive but the data centers and power supply are not ready. This delay directly affects whether chips can be transformed into usable computing power.

NVIDIA's strategy to increase GPU density per rack aims to enhance rack-level computing power through its scale-up architecture.

However, the Kyber solution used in the first generation of Rubin Ultra racks faces challenges related to PCB design and cooling. Consequently, the Oberon NVL72 design may continue to be used, with further expansion to the NVL576 scale via CPO or NPO interconnections. Increasing rack density concentrates demands on power supply, cooling, and interconnection in higher-specification data center designs.

Woofun AI data shows that HBM and CoWoS remain critical constraints, with AI chip HBM demand estimated at 48.618 billion Gb in 2027. Exhibit 3 indicates a CoWoS configuration requiring approximately 2.664 million wafers, while Exhibit 5 suggests a global CoWoS demand of around 2.694 million wafers. The market size for wafer revenue generated by AI computing chips is projected to be at least $58.8 billion. NVIDIA consumes the most CoWoS capacity with 1.222 million wafers, followed by AMD with 0.53 million wafers and Broadcom with 0.484 million wafers.

Uncertainty surrounds the Rubin Ultra's HBM configuration, which has not been finalized. Supply chain analyses suggest tiered specifications, with higher-end versions using HBM4e 8Hi and lower-end versions possibly using HBM4 12Hi or 8Hi. Morgan Stanley expects NVIDIA to decide by the end of the third quarter of 2026. This adjustment reflects pressures from HBM capacity shortages, rising memory costs, and varying workload demands. Exhibit 3 still assumes Rubin Ultra uses HBM4e 12Hi with 384GB per chip, meaning the 48.618 billion Gb demand may not fully reflect potential reductions. Micron's HBM4 is already in mass production, with HBM4E expected in 2027.

The shipment timeline for the Rubin series remains aggressive, with total shipments approaching 7 million units by 2027. This includes 5.92 million Rubin chips and 1.04 million Rubin Ultra chips, alongside 90,000 Rubin NVL72 racks. Rubin shipments are expected to increase in the third quarter of 2026, with rack deliveries beginning in the fourth quarter. The report notes that Blackwell inventory concerns were mostly buffer inventory, expected to be fully consumed by 2026. From the second half of 2026 to 2027, NVIDIA's supply chain must handle Blackwell digestion, Rubin shipment increases, HBM specification changes, and rack deliveries simultaneously.

Google's TPU expansion represents another significant growth driver, with shipments projected to rise from 3.7 million units in 2026 to 7.35 million units in 2027. This includes 4 million v8i units with Broadcom, 3 million v8t units with MediaTek, 150,000 v9 units, and 200,000 v7 units. TPU-related businesses could account for 7% to 8% of KYEC's revenue in 2026, rising above 10% in 2027. Including CPU and testing services, Google's demand may reach 10% to 15% of KYEC's revenue in 2027. The 3nm TPU developed with MediaTek will use Burn-in testing, while Google's CPU project requires Burn-in and system-level testing, increasing orders for testing facilities.

This integrated view highlights that 38GW is a stress test derived from chip shipments, not an accurate prediction of actual electricity consumption. Chinese AI GPU manufacturers may remain limited to 100Gb/s per channel due to domestic foundry constraints, relying on NPO interconnections, whereas NVIDIA favors CPO. These differences affect hypernode architectures, deployment costs, and system efficiency. Ultimately, the realization of AI computing power depends on the simultaneous readiness of HBM, CoWoS, testing, racks, and power supply.